The present invention concerns a wiring technique and, more in particular, it relates to an effective technique for applying a wiring technique to connection between a lower conductor layer and an upper conductor layer in a semiconductor integrated circuit device.
DRAM (Dynamic Random Access Memory) as a semiconductor memory device disclosed in U.S. Ser. No. 07/496,537 previously filed by the present applicant on Mar. 20, 1990 has a large capacity of 4M bit. A plurality of memory cells each for storing 1 bit information of the DRAM are arranged each at an intersection between a complementary data line and a word line and constituted with a serial circuit of an n-channel MOSFET for the selection of memory cell and a capacitance device for information storage.
The memory cell selecting n-channel MOSFET comprises a pair of n-type semiconductor regions used as source and drain regions, a gate insulation film, a gate electrode and a channel forming region. One of the n-type semiconductor regions is connected with the complementary data line. The gate electrode is integrally constituted along the direction of the width of the gate with the word line and connected electrically. The gate electrode and the word line are formed in the step of forming a first conductive layer in DRAM manufacturing process and it is formed, for example, with a polycrystalline silicone film. The other of the n-type semiconductor regions is connected to one of the electrodes of the information storage capacitance device.
The information storage capacitance device is constituted as a so-called stacked capacitor structure (STC structure) in which a lower layer electrode (one electrode), a dielectric film, an upper layer electrode (the other electrode) are respectively stacked successively. The lower layer electrode is connected to the other of the n-type semiconductor regions of the memory cell selecting n-channel MOSFET, and a peripheral portion thereof is extended on the gate electrode and on a word line connected to other adjacent memory cell. The lower layer electrode is formed in the step of forming a second conductive layer in the DRAM manufacturing process and is formed, for example, with a polycrystalline silicon film. The dielectric film is formed to the upper surface and the side of the lower layer electrode. The upper layer electrode is formed by way of the dielectric film on the lower layer electrode, constituted integrally with the upper layer electrode of the information storage capacitance device of other adjacent memory cells and connected electrically. That is, the upper layer electrode is used as a plate electrode in common with information storage capacitance devices of a plurality of memory cells. The upper electrode is formed in the step of forming a third conductive layer in the DRAM manufacturing process and is formed, for example, with a polycrystalline silicon film.
The information storage capacitance device adopting the stacked structure utilizes the upper surface and the side of the lower layer electrode as a charge accumulation region. In addition, since the charge accumulation region can be increased along the direction of the height by utilizing a step corresponding to the film thickness of each of the word lines, the charge accumulation amount of the charge accumulation capacitance device can be increased as a whole. That is, the information storage capacitance device of this type can reduce the generation of .alpha.-ray soft error or can improve the degree of integration by the area reduction of the memory cell.
The complementary data line is formed on an interlayer insulation layer formed on the entire area of a semiconductor substrate including that on the upper layer electrode of the information storage capacitance device of the memory cell, and connected with the memory cell through a connection hole formed in the interlayer insulation film. The interlayer insulation film is formed with a BPSG film (or PSG film) and reflow is applied to the BPSG film to flatten the surface of the film.
Since the use of the BPSG film applied with glass flow can moderate the step in the interlayer insulation film, it can prevent disconnection failure of the complementary data line.
Further, the complementary data line is formed by using an etching mask (photoresist mask) formed by photolithography and applying etching to a previously formed wiring material. Since the use of the BPSG film and the reflow technique can flatten the surface of the interlayer insulation film and moderate the stepped configuration in the region in which the wiring material is removed by etching, it can prevent an undesired phenomenon that the wiring material is not removed in this region. That is, use of the BPSG film applied with reflow can improve the patterning accuracy of the complementary data line.